As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Copper has increasingly become the metal of choice for fabricating interconnects in integrated circuits using a damascene process.
Interconnect layers continue to decrease in line width and are spaced closer together in order to attain increased density, faster performance, and lower cost. To further improve performance, dielectric materials having lower dielectric constants (also referred to as k-value) are employed in interconnect layers. However, lower k-values result in dielectric materials with higher porosity and lower density. As porosity increases, the internal pore-structure of the dielectric matrix can become more interconnected. This high porosity combined with interconnected pore volume can allow materials, in particular copper, to diffuse or penetrate through low k-value dielectric materials. Accordingly, defects and failure mechanisms can result, which can degrade performance reduce the operational lifetime of devices, and even lead to complete device failure. Another problem with porous low k-value dielectric materials due to the high porosity and low density of the materials is that they tend to have irregular or non-smooth sidewalls after features such as trenches or vias have been etched into or through them. As a consequence, subsequently formed and/or deposited materials form irregularly along sidewalls of the low k-value dielectric layers. Thus, for example, forming copper diffusion barrier layers with a uniform thickness along sidewalls of low k-value dielectric layers can be problematic due to the irregularities of the low k-value dielectric layer sidewalls.
What is needed are devices and methods that employ low k-value dielectric materials within copper based interconnect structures and also mitigate problems, such as those described above, that result from employing the low k-value dielectric materials.